FPGA MD5 Cracker

June 16th, 2009 by Patchy

For my Digital Systems Laboratory (ECE 385) at the University of Illinois I had to do a final project using a field-programmable gate array (FPGA). My partner and I designed a hardware implementation of the MD5 algorithm and used it to crack MD5 password hashes. A FPGA allows you to prototype large digital circuits by utilizing a hardware description language such as VHDL. The FPGA enabled us to create a large hardware system dedicated to cracking MD5 Passwords. The FPGA we used was the Altera DE2 Development Board with the Cyclone II chip, and we were able to fit sixteen parallel MD5 Cracking units onto the FPGA. Each unit is able to produce a MD5 hash in 68 clock cycles, and since the FPGA has a clock rate of 50 MHz this system is able to produce over 44 million hashes a minute. The MD5 hash is inputted by the user through a keyboard, and if the system finds a match, the clear text password is displayed on a VGA monitor. Full Scale Video Here
Download Here
Download FPGA MD5 Cracker Project Files

Posted in Vblog | 6 Comments »

6 Responses

1. MarianG Says:
   June 22nd, 2009 at 4:36 am

   That thing ROCKS.
   I have only one question.
   Are you guys going to improve it?
   * Change the board to fit more Cracking units;
   * …

2. overide Says:
   June 22nd, 2009 at 1:00 pm

   cool project

3. Patchy Says:
   June 22nd, 2009 at 3:41 pm

   @MarianG: This is the third revision of this project. The first version only fit two cracking units, then 8 units. I wanted to use two or more boards but I only had 4 weeks to do the project. I probably won’t expand the project anymore unless I can get a much better FPGA because the Cyclone II just doesn’t have a fast enough clock rate or enough space to be able to compete with a GPU.

4. XSSer Says:
   July 1st, 2009 at 10:31 pm

   hey pathcy i need to get talk to u

5. ssaadd Says:
   July 6th, 2009 at 2:19 am

   hi, i hv a question, can we use other boards like “xilinx spartan 3 xc3s200″? reply soon plzzzz.

6. Patchy Says:
   July 7th, 2009 at 6:51 pm

   Since it is programmed in VHDL it should work on a xilinx FPGA, but I do not know if that FPGA has the proper amount of space to fit the project.

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