FPGA MD5 Cracker

For my Digital Systems Laboratory (ECE 385) at the University of Illinois I had to do a final project using a field-programmable gate array (FPGA). My partner and I designed a hardware implementation of the MD5 algorithm and used it to crack MD5 password hashes. A FPGA allows you to prototype large digital circuits by utilizing a hardware description language such as VHDL. The FPGA enabled us to create a large hardware system dedicated to cracking MD5 Passwords. The FPGA we used was the Altera DE2 Development Board with the Cyclone II chip, and we were able to fit sixteen parallel MD5 Cracking units onto the FPGA. Each unit is able to produce a MD5 hash in 68 clock cycles, and since the FPGA has a clock rate of 50 MHz this system is able to produce over 44 million hashes a minute. The MD5 hash is inputted by the user through a keyboard, and if the system finds a match, the clear text password is displayed on a VGA monitor.
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Download FPGA MD5 Cracker Project Files